Integrated circuits have achieved widespread use in that they are capable of reducing the space required to achieve a given electrical function, with an attendant increase in performance including a reduction in power requirements. In order for integrated circuits to conveniently interface with other integrated circuits and other types of electronic circuitry, certain industry-wide input/output (I/O) specifications have been developed. One example is the transistor-transistor logic (TTL) standard in which a supply voltage of 5 volts (nominal) is applied to a device. An input signal associated with a logical zero has a maximum voltage of approximately 0.7 volts and a logical one input level has a minimum voltage of approximately 2 volts. This TTL specification also requires that an integrated circuit provide an output voltage of at least approximately 2.4 volts associated With a logical one output signal, and an output voltage of not more than approximately 0.4 volts associated with a logical zero output level.
Current advancements in integrated circuit technology are spurring an evolution to lower voltage devices than the TTL standard. For example, one current trend is to develop integrated circuits utilizing 3 or 3.3 volt power supplies. In the future, even lower voltage devices (such as 2.4 volt devices) will be developed. Among the reasons for moving to lower voltage integrated circuits are a need to reduce system power without a corresponding tradeoff in performance.
Given the large number of TTL device types, it would be desirable to provide lower voltage devices which are capable of withstanding excessive voltages applied to their input and output pins from external sources, for example, if they are inadvertently or intentionally used with TTL devices or interfaces. Thus, for example, for a 3.0 volt device in which a high output voltage of approximately 3 volts corresponds to a logical one output signal, it would be very beneficial if the device were able to withstand a TTL logical one voltage level of approximately 5 volts applied to the output terminal, without consuming excessive power or incurring damage. Similarly, it would be very beneficial if a 2.4 volt device were able to withstand a logical one level of approximately 5 volts (TTL standard) or approximately 3.0 volts (for a 3.0 volt device) logical one signals apply to the output terminal. U.S. patent application Ser. No. 07/994,783, filed Dec. 22, 1992 discloses certain low voltage input and output circuits with overvoltage protection, allowing such a lower voltage device to operate with higher voltage devices without deleterious effects.
FIG. 1 is a block diagram depicting a first circuit 101 connected to bus 103 via protection circuit 102. In this general form of the present invention, circuit 101 may be a 3 volt integrated circuit device, for example, and bus 103 may be a typical prior art TTL level bus, operating with voltages up to about a nominal 5 volt level. Protection circuit 102, as taught by this invention and more fully described in the following examples, serves to provide an interface between circuit 101 and bus 103 allowing circuit 101 to be powered down without drawing excessive current or deleteriously affecting the signal levels on bus 103.
Certain prior art examples of such circuits 102 are described in Electronic Design, Aug. 20, 1992, page 42. The prior art technique described in that reference article includes the use of a pass transistor connected between the output of the circuit and the bus (or bonding pad which is in turn connected to the bus), with the gate of the pass transistor being connected to the 3 volt VCC level of circuit 101. An alternative prior art circuit described in that reference article utilizes two pass transistors, one connected between the bonding pad and the pull-up transistor, and the other connected between the bonding pad and the pull-down transistor, each having their gates connected to the 3 volt VCC level of circuit 101.
The prior art circuits thus described suffer from a number of disadvantages. First, and foremost, they do not provide adequate protection between a powered down circuit and the bus in that the gate of the pass transistors of such prior art circuits are connected to the VCC of the circuit. When powered down, this VCC is 0 volts, in which event the pass transistor remains turned off and the full voltage of the bus appears across the gate oxide of the pass transistor. As an example, when circuit 101 is a 3 volt circuit, the maximum gate oxide voltage allowable is approximately 4.6 volts if the circuit is optimized for speed and power performance. However, as previously described, the bus may be a TTL level bus, in which its voltage may rise as high as 5 volts (actually, as high as approximately 7 volts considering overshoots which are typically encountered on TTL buses), which is clearly in excess of the maximum gate oxide voltage of the 3 volt process used to fabricate circuit 102 as part of an integrated circuit also including circuit 101.
Other prior art circuits utilize an interface circuit capable of detecting overvoltages but such overvoltage detection circuits operate with a certain amount of delay, meaning that the circuit cannot properly respond to fast transient voltage changes, which allows excessive voltages to appear across the gate oxide of the pass transistor.
Clearly each of these prior art attempts to allow a lower voltage circuit to interface with a higher voltage bus is inadequate to protect the lower voltage circuit from transient voltages, particularly when the lower voltage circuit 101 is powered down while connected to an active bus 103.